You will work in the Signal Power Integrity Engineering (SPIE) team for the ASDG's SOC Hard IP Enabling Group (HIP). You will ensure the Power Integrity specifications are met for all the Hard IP blocks.In this position, you will be responsible for providing the Power Integrity Reference Design Guidelines (RDG), along with the models to the Hard IP customers. Your responsibilities will include but not be limited to:
- Working closely with the ...
Intel - 17 months ago
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